`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
    genvar i;
	assign S[0]=A_in[0]^B_in[0]^C_1;
	wire [3:0]C;
	assign C[0] = (A_in[0] & B_in[0]) + ((A_in[0] ^ B_in[0]) & C_1);
    wire [3:1]S_r;
    
	generate 
		for(i=1;i<4;i=i+1)begin:L
			assign S_r[i]=A_in[i]^B_in[i]^C[i-1];
			assign C[i]=(A_in[i]&B_in[i])|(A_in[i]^B_in[i]&C[i-1]);
		end
	endgenerate
    assign S[3:1]=S_r[3:1];
	assign CO=C[3];
endmodule